Optimizing SSDs with Software Defined Flash, Part 2

Author: Rahul Advani

In my last post, I talked about the increasing use of enterprise Solid-State Drives (SSDs) and the many different requirements they must be tuned for based on data center application needs. The dilemma for the SSD makers is how to meet these disparate needs while still offering affordable solutions to end users. Supporting these disparate requirements that span cold storage to high-performance SSDs for database applications cost-effectively requires a well-planned, flexible silicon architecture that will allow for software defined solutions.  These solutions need to support software optimizations based around (to name a few):

  • Different densities and over-provisioning NAND levels
  • Different types of NAND (SLC/MLC/TLC) at different nodes
  • Different power envelopes
  • Different amounts of DRAM
  • Often need to support Toggle and ONFI, in order to maintain flexibility of NAND use

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Optimizing SSDs with Software Defined Flash, Part 1

Author: Rahul Advani

With the rise of big data applications like in-memory analytics and database processing where performance is a key consideration, enterprise Solid-State Drive (SSD) use is growing rapidly. IDC forecasts the enterprise SSD segment to be a $5.6 billion market by 20151.  In many cases, SSDs are used as the highest level of a multi-tier storage system, but there is also a trend towards all-SSD storage arrays  as price performance metrics, including dollar per IOP ($/IOP) and dollar per workload ($/workload) make it an attractive option.

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Project Donard: Peer-to-Peer Communication with NVM Express Devices, Part 1

Author: Stephen Bates (@stepbates)

IntroductionDonard

Last month I attended Flash Memory Summit (FMS) 2014 in Santa Clara, California. FMS is probably the biggest conference and exposition of NVM technology. It combines technical tracks with a huge exposition and is a great place to catch up and hobnob with like-minded experts in NVM.

PMC was very well represented at FMS. We presented eight technical papers, gave a keynote speech and launched our Flashtec NVRAM product. I gave a talk entitled “Accelerating Data Centers Using NVMe and CUDA” which is based on a PMC CTO project codenamed Donard. In this blog post I want to dig a little deeper into the paper I presented and some of the implications of this for acceleration in data center (DC) environments.

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The Latest on NVMe Open Source Drivers for Windows and VMWare

Author: Kwok Kong

NVM Express (NVMe) is the scalable host controller interface designed for PCI Express®(PCIe®)-based solid state drives and defines the host driver interface. PMC has contributed to the NVMe specification since its inception and continues to work with industry leaders to create a robust NVMe driver ecosystem.

PMC helped drive the initial development of the first NVMe Open Source Windows driver with key partners in 2011. The first major release of this driver was completed in Q2 2012.  PMC continues to chair this working group, which has since accomplished four major releases of the Windows driver.  The next release, version 1.4, is scheduled for Q4 2014 with the major focus on stability and ensuring certification with the Windows Hardware Certification Kit (HCK), which will enable this driver to be digitally signed by WHQL. The release package may be downloaded from https://www.openfabrics.org/index.php/developer-tools/nvme-windows-development.htmlContinue reading

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Soft-Decoding in LDPC based Next-Generation SSD Controllers

Author: Stephen Bates

Introduction

In my last post, I Information Concepttalked about how we can control the parameters of Low-Density Parity-Check (LDPC) error correction codes in order to manage the latency associated with reads from a Solid-State Drive (SSD). However, we only looked at the iterations associated with a single decode of the LDPC codeword. In this post, we will take a look at what happens when that initial decode fails and how soft-information can be used to recover the data on the SSD.

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Latency in LDPC-based Next-Generation SSD Controllers

Author: Stephen Bates

Latency Variability

In my last post I talked about the transition to Low-Density Parity-Check (LDPC) Error Correction Codes (ECCs) in enterprise SSD controllers. I hinted that this transition has some interesting implications for the latency of next-generation SSD controllers and I wanted to expand on that topic in this post.Storage_title_image

The latency associated with LDPC ECC in SSDs comes from three main sources:

  1. The LDPC encoding process.
  2. The LDPC decoding associated with the first read of the data on the NAND flash.
  3. The LDPC decoding associated with subsequent reads of the data on the NAND flash.  Continue reading
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Transitioning SSDs to LDPC Error Correction Codes

Author: Stephen Bates

The Transition

I’m sure many of you readiStorage_title_imageng this blog are aware there is a transition occurring in terms of the type of Error Correction Codes (ECCs) being used inside SSD controller chips. Traditionally Bose-Chaudhuri-Hocquenghem (BCH) were used, and they were more than adequate for large geometry NAND flash. However, the demand for cheaper and denser NAND flash means that BCH is no longer adequate and, in the search for alternatives, most of us are settling on Low Density Parity Check (LDPC) codes.

In this post, I want to talk a little about what this transition means and some implications it has for something we at PMC term Software Defined Flash. For more background on what an LDPC code is, check out Kent Smith’s great post.

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